The present invention in general relates to a clock generator circuit. More particularly, this invention relates to a clock generator circuit used in semiconductor devices and that has a high precision correction of frequency with low power consumption.
A conventional clock generator circuit disclosed in Japanese Patent Application Laid-Open No. 11-186899 is shown in FIG. 8. This clock generator circuit 100 comprises an oscillator 102, a load-value change-timing generator 103, a variable counter 104, and a load-value controller 105.
The oscillator 102 generates an original oscillation clock 102a, and outputs this clock to the load-value change-timing generator 103 and the variable counter 104.
The load-value change timing generator 103 counts in synchronism with the original oscillation clock 102a input from the oscillator 102 to a clock input terminal. Then, based on the count value, the load-value change timing generator 103 makes a decision to be supplied to the variable counter 104 concerning a load value, and outputs a result of this decision to the load-value controller 105 as a load-value change timing 103a. 
The variable counter 104 counts in synchronism with the original oscillation clock 102a input from the oscillator 102 to a clock input terminal. When the counting reaches a predetermined count value, the variable counter 104 outputs a carry signal 104a. 
According to this conventional clock generator circuit, when the period of the oscillator has varied due to a change in the operation environment such as, for example, a change in temperature, or a change in voltage, the output period of the carry signal 104a also varies. As a result, it becomes difficult to obtain the necessary period.
Further, as the correction precision of the frequency is determined based on the frequency of the oscillator, it is impossible to carry out a fine adjustment.
Further, as the oscillator is always operating, this has a problem of wasteful power consumption.
The clock generator circuit of this invention comprises an oscillation circuit which generates a first clock signal, a first timer which counts the first clock signal, and a ring oscillator which generates a second clock signal. Furthermore, there is provided a second timer that is input with an overflow signal of the first timer, and that counts the second clock signal. Furthermore, there is provided a third timer that has a reload register for storing an inverted value of each bit of the second timer, and that generates a third clock signal. This third timer counts the inverted value, and sets the count value in the reload register.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.